1. Field of the Invention
The present invention relates to a method for forming a resist pattern used in fabricating a semiconductor device and the like.
2. Description of the Related Art
Presently, a reduced projection aligner is used as an aligner in the process for fabricating semiconductor devices. The reduced projection aligner allows a high alignment accuracy to be realized in addition to a high resolution because light (ultraviolet rays) passing through a reticle is reduced through a reduced optical system. However, with the recent advancement in the micronization of LSIs, a higher alignment accuracy is required.
It is important to improve the alignment accuracy, reduce the minimum working dimensions in a lithographic process, and increase the integration of the large scale integrated circuit because it is necessary to leave a margin in anticipation of a misalignment. For instance, it is necessary to provide an alignment margin in an underlying wiring pattern in view of the alignment accuracy of a device to prevent a contact hole from shifting from the underlying wire that connects two layers of the upper and lower wiring layers via the contact hole in designing an LSI. Because the alignment margin needs to be thus provided, it is difficult to dispose the underlying wiring pattern closely.
This point will be explained with reference to FIG. 1. As shown in FIG. 1, an underlying wire 160a is designed widely in the vertical and horizontal directions to leave a margin for alignment error for the overlapping contact hole (via hole) 160b on the underlying wire 160a. The contact hole 160b therefore remains positioned on the underlying wire 160a even when a misalignment occurs.
However, the domain of the alignment margin is originally a wasteful domain and poses a problem in the advancement of the integration. It also poses a problem in the performance of the RC delay due to the increase of capacity between wires because the distance between the wires is narrow at the spot where there is the alignment margin.
Meanwhile, it has been impossible to eliminate a misalignment because the alignment is carried out by using an alignment mark. There has been proposed a method of aligning the upper and lower layers in the fashion of self-alignment in the aspect of processing. This method will be explained below by exemplifying the self-alignment of an upper embedded type wire with an underlying contact hole with reference to FIGS. 2A, 2B and 2C.
At first, as shown in FIG. 2A, an insulating layer 162 is formed on an underlying layer 161 and an insulating layer (etching stopping layer) 163 is formed on the insulating layer 162. The stopping layer 163 acts as a layer for stopping RIE (Reactive Ion Etching) in etching an insulating layer 164 to be formed later by means of RIE. The stopping layer 163 is etched to selectively remove a contact hole including an alignment margin thereof.
Next, the insulating layer 164 is formed on the stopping layer 163 and a resist pattern 165 for forming a wire is formed on the insulating layer 164 as shown in FIG. 2B. Then, the insulating layers 164 and 162 are etched by means of RIE to create a groove for forming the wire therein by using the resist pattern 165 as a mask as shown in FIG. 2C.
At this time, while the etching is stopped on the surface of the stopping layer 163 where the contact hole is not created, the etching advances at the part overlapping with the pattern for forming the wire because the stopping layer 163 has been removed where the contact hole exists, so that the contact hole which aligns with the wiring groove is formed in the fashion of self-alignment. Finally, a wiring metal layer (not shown) is filled in the wiring groove and the contact hole, thus completing the wiring.
It is possible to align the upper wire with the underlying contact hole in the fashion of self-alignment in the above-mentioned method applied in the embedded type wiring. However, the lower the pattern, the finer the pattern needs to be in the scaling rule of LSIs, and the higher the pattern, the looser the scaling rule is. Therefore, it is necessary to align the upper pattern accurately with the finer lower pattern. It is difficult, however, to achieve as close a match as possible by using the method described above.
Meanwhile, there is a case in a process of fabricating a MOS transistor when a film is formed on an underlying structure in which a gate is formed and the film should be patterned into a predetermined pattern. It is also difficult, however, to pattern the film without misalignment with this gate in such a case, and an alignment margin is required even though it hampers the integration of LSIs.
As a method for forming an upper pattern on an underlying pattern in the fashion of self-alignment, a method has been disclosed in Japanese Patent Disclosure No. 59-124722, for example. According to this method, a resist which is sensitive to a secondary X-ray is applied on a metal wiring structure formed on a ceramic substrate. An aperture portion of the resist is created only on the metal wire in the fashion of self-alignment by shielding the secondary X-ray emitted from the substrate by the metal wire when X-ray is irradiated from the top of the resist.
This method was invented to form a wiring layer of a ceramic package and cannot be applied to a semiconductor integrated circuit having a contact pattern of arbitrary shape because the contact hole needs to be created at an arbitrary position of an interlayer insulating layer covering an underlying wiring pattern in the semiconductor integrated circuit device.
Accordingly, it is an object of the present invention to provide a method for forming a resist pattern which allows the patterns to be align as close as possible.